The present invention relates to a solid-state image pickup device incorporating an analog/digital converter (hereinafter referred to as ADC), and in particular, relates to a solid-state image pickup device incorporating an ADC that can be arranged in a limited space.
Although film-type cameras have been mainstream in conventional cameras, digital cameras have recently been replacing them. Further, the enhancement of the image quality of digital cameras is remarkable, and the latest models of digital cameras perform better than film cameras. The types of digital cameras include CCD (Charge Coupled Device) and CMOS (Complementary Metal Oxide Semiconductor) image sensors. In terms of enhancing the performance of cameras, there is increasing attention to the CMOS image sensor in which CMOS devices are more easily mounted.
The CMOS image sensor includes two types of image sensors which are an analog image sensor and a digital image sensor. Although each image sensor has its merits and demerits, there are large expectations for the digital image sensor in terms of data processing speed. Specifically, the use of the digital image sensor enables not only moving image shooting but also various applications in combination with image processing of a subsequent stage.
For example, in the case of photographing at the moment when a ball hits a tennis racket or the close-up face of a child who crosses the finish line running around a playground at an athletic meet, by simply pointing a camera toward it the camera can automatically determine a photo opportunity and automatically trigger the shutter. In order to achieve such processing, it is necessary to transfer a shot image to an image processing IP (Intellectual Property) in an instant and to convert shot information (analog information) into image processing information (digital information).
Under such circumstances, ADCs for digital cameras have been actively researched and developed. The biggest problem with the CMOS image sensor is that the conversion of all pixel information into digital values requires a large amount of data processing. For example, if 10 million pixels are processed simply by one ADC at a typical moving image processing rate of 30 fps (frames per second), one-pixel information needs to be A/D-converted and transferred within 3 ns, which is unrealistic. For this reason, the signals of pixels arranged in a matrix are captured in ADCs through vertical readout lines arranged in respective columns, and the signals of pixels of a selected row are sequentially A/D-converted. Related techniques are disclosed in Japanese Unexamined Patent Publication No. 2008-098722 and Japanese Unexamined Patent Publication No. 2006-352597 as follows.
Japanese Unexamined Patent Publication No. 2008-098722 discloses a technique for enabling high-speed, high-resolution AD conversion in a CMOS image sensor in which column-parallel ADCs are mounted. In the CMOS image sensor in which column-parallel ADCs are mounted, with reference voltages Vref1 to Vref4 and a reference voltage Vref5 having different slopes, a column processing circuit includes a comparison circuit for comparing an output voltage Vx of a unit pixel with the reference voltages Vref1 to Vref4 and a comparison circuit for comparing the reference voltages Vref1 to Vref4 with the reference voltage Vref5. The operations of the two comparison circuits and an up/down counter enable high-resolution AD conversion to be performed at high speed.
Japanese Unexamined Patent Publication No. 2006-352597 discloses a technique developed by focusing on the point that an AD conversion time is dependent on a count period, particularly the second count period, which occupies most of the AD conversion time, thus making it difficult to reduce the AD conversion time. In a CMOS image sensor in which column-parallel ADCs are mounted, before the second AD conversion a signal voltage Vx of a column signal line is level-determined using a plurality of determination voltages in the AD conversion range, and based on the determination result, from among a plurality of reference voltages RAMP1 to RAMPn a reference voltage RAMP suitable for the signal voltage Vx of the column signal line is selected for AD conversion, thereby reducing the second AD conversion time.